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W25Q128BV
7.2.24 32KB Block Erase (52h)
The Block Erase instruction sets all memory within a specified block (32K-bytes) to the erased state of all
1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase
Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low
and shifting the instruction code “52h” followed a 24 -bit block address (A23-A0) (see Figure 2). The Block
Erase instruction sequence is shown in Figure 22.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done
the Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block Erase
instruction will commence for a time duration of t BE 1 (See AC Characteristics). While the Block Erase
cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of
the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is
finished and the device is ready to accept other instructions again. After the Block Erase cycle has
finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase
instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB,
BP2, BP1, and BP0) bits (see Status Register Memory Protection table).
/CS
Mode 3
0
1
2
3
4
5
6
7
8
9
29
30
31
Mode 3
CLK
Mode 0
Instruction (52h)
24-Bit Address
Mode 0
DI
(IO 0 )
23
*
22
2
1
0
DO
(IO 1 )
* = MSB
High Impedance
Figure 22. 32KB Block Erase Instruction Sequence Diagram
Publication Release Date: October 03, 2013
- 43 -
Revision H
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